Как изменить несколько раз переменную в VHDL?

Question

Username @dalv_happy

VHDL

Как изменить несколько раз переменную в VHDL?

Добрый день.
На языке vhdl необходимо реализовать
Q1 = (I1 & I2 & I3 | I3 & I4 & I5) & T2
Где Q — выходное значение,
I — Входные сигналы,
T2 — таймер.

Делал следующим образом через after, но мне нужно вывести значение T2, т.е. до after оно было 0, после того как after сработал через 5 секунд, мне нужно на временной диаграмме отобразить изменения т.е. 1.
Как это можно сделать?

architecture logic_behavior of logic is
	constant T1 : time := 2000 ms;
	constant T2 : time := 5000 ms;
	constant T3 : time := 7000 ms;
	
	signal Q1_2: std_logic;

	signal Q4_I1: std_logic;
	signal Q4_I2: std_logic;
	signal Q4_I3: std_logic;
	
	signal TT2_I: std_logic := '0';	
	
begin
	Q1_2 <= (I1 and I2 and I3) or (I3 and I4 and I5) after T2;	

	Q1 <= Q1_2; --write direct output
	Q2 <= (not Q1_2); --write inverse output
	Q3 <= (not I1) or (not I2) or (not I3) or (not I4) after T3;

	Q4_I1 <= I1 after T1;
	Q4_I2 <= I2 after T2;
	Q4_I3 <= I3 after T3;
	Q4 <= Q4_I1 or Q4_I2 or Q4_I3;
end logic_behavior;

Результат:

logic.vhdl

library ieee;
use ieee.std_logic_1164.all;

--Description interface the system
entity logic is
	port (
		I1: in std_ulogic; --first_input
		I2: in std_ulogic; --second_input
		I3: in std_ulogic; --second_input
		I4: in std_ulogic; --second_input
		I5: in std_ulogic; --second_input
		Q1: out std_ulogic; --direct outputs
		Q2: out std_ulogic; --inverse outputs
		Q3: out std_ulogic; --inverse outputs
		Q4: out std_ulogic; --inverse outputs
		TT2: out std_ulogic --inverse outputs
	);
end logic;

--Description behavior the system
architecture logic_behavior of logic is
	constant T1 : time := 2000 ms;
	constant T2 : time := 5000 ms;
	constant T3 : time := 7000 ms;
	
	signal Q1_2: std_logic;

	signal Q4_I1: std_logic;
	signal Q4_I2: std_logic;
	signal Q4_I3: std_logic;
	
	signal TT2_I: std_logic := '0';	
	
begin
	Q1_2 <= (I1 and I2 and I3) or (I3 and I4 and I5) after T2;	
	--TT2 <= '0' after 0 ms, '1' after T2;
	--if (TT2_I = '0') then
		--TT2 <= '0';
	--else
		--TT2 <= '1';
	--end if;
	Q1 <= Q1_2; --write direct output
	Q2 <= (not Q1_2); --write inverse output
	Q3 <= (not I1) or (not I2) or (not I3) or (not I4) after T3;

	Q4_I1 <= I1 after T1;
	Q4_I2 <= I2 after T2;
	Q4_I3 <= I3 after T3;
	Q4 <= Q4_I1 or Q4_I2 or Q4_I3;
end logic_behavior;

logic_tb.vhdl

-- code testing 'logic'
library ieee;
use ieee.std_logic_1164.all;

--Description interface the system. As this is a test file, 
--the system interface is always empty
entity logic_tb is
	
end logic_tb;

--Description behavior
architecture logic_behavior_test of logic_tb is
	
	--Description of test component
	component logic
		port (
			I1: in std_ulogic; --first_input
			I2: in std_ulogic; --second_input
			I3: in std_ulogic; --second_input
			I4: in std_ulogic; --second_input
			I5: in std_ulogic; --second_input
			Q1: out std_ulogic; --direct outputs
			Q2: out std_ulogic; --inverse outputs
			Q3: out std_ulogic; --inverse outputs
			Q4: out std_ulogic; --inverse outputs
			TT2: out std_ulogic --inverse outputs
		);
	end component;
	--reservation of all used signals
	signal I1, I2, I3, I4, I5, Q1, Q2, Q3, Q4, TT2: std_ulogic;
	
begin
	--mapping signal with interface system
	half_adder: logic port map(I1 => I1, I2 => I2, I3 => I3, I4 => I4, I5 => I5, Q1 => Q1, Q2 => Q2, Q3 => Q3, Q4 => Q4, TT2 => TT2);
	
	--process testing
	process begin		
		
		I1 <= '0';
		I2 <= '0';
		I3 <= '0';
		I4 <= '0';
		I5 <= '0';
		TT2 <= '0';
		wait for 20000 ms;

		I1 <= '0';
		I2 <= '0';
		I3 <= '0';
		I4 <= '0';
		I5 <= '1';
		wait for 20000 ms;

		I1 <= '0';
		I2 <= '0';
		I3 <= '0';
		I4 <= '1';
		I5 <= '0';
		wait for 20000 ms;

		I1 <= '0';
		I2 <= '0';
		I3 <= '0';
		I4 <= '1';
		I5 <= '1';
		wait for 20000 ms;

		I1 <= '0';
		I2 <= '0';
		I3 <= '1';
		I4 <= '0';
		I5 <= '0';
		wait for 20000 ms;

		I1 <= '0';
		I2 <= '0';
		I3 <= '1';
		I4 <= '0';
		I5 <= '1';
		wait for 20000 ms;

		I1 <= '0';
		I2 <= '0';
		I3 <= '1';
		I4 <= '1';
		I5 <= '0';
		wait for 20000 ms;

		I1 <= '0';
		I2 <= '0';
		I3 <= '1';
		I4 <= '1';
		I5 <= '1';
		wait for 20000 ms;

		I1 <= '0';
		I2 <= '1';
		I3 <= '0';
		I4 <= '0';
		I5 <= '0';
		wait for 20000 ms;

		I1 <= '0';
		I2 <= '1';
		I3 <= '0';
		I4 <= '0';
		I5 <= '1';
		wait for 20000 ms;

		I1 <= '0';
		I2 <= '1';
		I3 <= '0';
		I4 <= '1';
		I5 <= '0';
		wait for 20000 ms;

		I1 <= '0';
		I2 <= '1';
		I3 <= '0';
		I4 <= '1';
		I5 <= '1';
		wait for 20000 ms;

		I1 <= '0';
		I2 <= '1';
		I3 <= '1';
		I4 <= '0';
		I5 <= '0';
		wait for 20000 ms;

		I1 <= '0';
		I2 <= '1';
		I3 <= '1';
		I4 <= '0';
		I5 <= '1';
		wait for 20000 ms;

		I1 <= '0';
		I2 <= '1';
		I3 <= '1';
		I4 <= '1';
		I5 <= '0';
		wait for 20000 ms;

		I1 <= '0';
		I2 <= '1';
		I3 <= '1';
		I4 <= '1';
		I5 <= '1';
		wait for 20000 ms;

		I1 <= '1';
		I2 <= '0';
		I3 <= '0';
		I4 <= '0';
		I5 <= '1';
		wait for 20000 ms;

		I1 <= '1';
		I2 <= '0';
		I3 <= '0';
		I4 <= '0';
		I5 <= '1';
		wait for 20000 ms;

		I1 <= '1';
		I2 <= '0';
		I3 <= '0';
		I4 <= '1';
		I5 <= '1';
		wait for 20000 ms;

		I1 <= '1';
		I2 <= '0';
		I3 <= '0';
		I4 <= '1';
		I5 <= '1';
		wait for 20000 ms;

		I1 <= '1';
		I2 <= '0';
		I3 <= '1';
		I4 <= '0';
		I5 <= '1';
		wait for 20000 ms;

		I1 <= '1';
		I2 <= '0';
		I3 <= '1';
		I4 <= '0';
		I5 <= '1';
		wait for 20000 ms;

		I1 <= '1';
		I2 <= '0';
		I3 <= '1';
		I4 <= '1';
		I5 <= '1';
		wait for 20000 ms;

		I1 <= '1';
		I2 <= '0';
		I3 <= '1';
		I4 <= '1';
		I5 <= '1';
		wait for 20000 ms;

		I1 <= '1';
		I2 <= '1';
		I3 <= '0';
		I4 <= '0';
		I5 <= '1';
		wait for 20000 ms;

		I1 <= '1';
		I2 <= '1';
		I3 <= '0';
		I4 <= '0';
		I5 <= '1';
		wait for 20000 ms;

		I1 <= '1';
		I2 <= '1';
		I3 <= '0';
		I4 <= '1';
		I5 <= '1';
		wait for 20000 ms;

		I1 <= '1';
		I2 <= '1';
		I3 <= '0';
		I4 <= '1';
		I5 <= '1';
		wait for 20000 ms;

		I1 <= '1';
		I2 <= '1';
		I3 <= '1';
		I4 <= '0';
		I5 <= '1';
		wait for 20000 ms;

		I1 <= '1';
		I2 <= '1';
		I3 <= '1';
		I4 <= '0';
		I5 <= '1';
		wait for 20000 ms;

		I1 <= '1';
		I2 <= '1';
		I3 <= '1';
		I4 <= '1';
		I5 <= '1';
		wait for 20000 ms;

		I1 <= '1';
		I2 <= '1';
		I3 <= '1';
		I4 <= '1';
		I5 <= '1';
		wait for 20000 ms;

		
		wait;
		
	end process;
end logic_behavior_test;